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[VHDL-FPGA-Verilog] Altera_DDR_controller_core

Description: Altera DDR SDRAM控制器完整Verilog代码包，包括Verilog源代码，Doc说明文档，仿真DDR芯片模型，仿真testbench等-Altera DDR SDRAM Controller. Verilog source codes, description documents, DDR verilog model and simulation testbench are all included.
Platform: | Size: 752640 | Author: 沈志 | Hits:

[VHDL-FPGA-Verilog] sdr_sdram

Description: sdram控制器，verilog语言写的-sdram controller, verilog language to write
Platform: | Size: 2048 | Author: xwj | Hits:

[VHDL-FPGA-Verilog] X-HDL

Description: 一款可以在verilog和VHDL之间互换的工具，经测试，暂无bug-A verilog and VHDL can be exchanged between the tools, tested, no bug
Platform: | Size: 3962880 | Author: 邵文熙 | Hits:

[VHDL-FPGA-Verilog] sdram_mdl

Description: verilog编写的对SDRAM的控制的源代码，开发FPGA/CPLD-verilog SDRAM write control of the source code, development FPGA/CPLD
Platform: | Size: 2286592 | Author: luoqv | Hits:

[VHDL-FPGA-Verilog] SDRAM

Description: verilog语言对SDRAM读写时序的描述，采用状态机结构实现的读写功能-timing of the SDRAM read and write verilog language description, a state machine structure to achieve read and write capabilities
Platform: | Size: 3072 | Author: | Hits:

[VHDL-FPGA-Verilog] DDR-SDRAM_IP_core

Description: DDR-SDRAM接口模块verilog源代码，可用作IP核使用，已在FPGA上验证-DDR-SDRAM interface module verilog source code, can be used as IP cores to use, proven
Platform: | Size: 474112 | Author: zyy | Hits:

[VHDL-FPGA-Verilog] SDR_SDRAM_IP

Description: SDR SDRAM 控制器，Altera官网重要资料。内涵说明文档，和VHDL与Verilog两种设计IP。-SDR SDRAM controller from Altera
Platform: | Size: 2360320 | Author: peteryu010 | Hits:

[VHDL-FPGA-Verilog] 83399055ref-sdr-sdram-verilog

Description: Summary: InterPreTS (Interaction Prediction through Tertiary Structure) is a web-based version of our hod for predicting protein-protein interactions (Aloy and Russell, 2002, Proc. Natl Acad. Sci. USA, 99, 5896-5901). Given a pair of query sequences, we first search for homologues in a database of interacting domains (DBID) of known three-dimensional complex structures. Pairs of sequences homologous to a known interacting pair-Summary: InterPreTS (Interaction Prediction through Tertiary Structure) is a web-based version of our method for predicting protein-proteiinteractions (Aloy and Russell, 2002, Proc. Natl Acad. Sci. USA, 99, 5896-5901). Given a pair of query sequences, we first search for homologues in a database of interacting domains (DBID) of known three-dimensional complex structures. Pairs of sequences homologous to a known interacting pair
Platform: | Size: 718848 | Author: wx | Hits:

[VHDL-FPGA-Verilog] Sdram_Control_4Port

Description: 用verilog写的sdram的控制，进行sdram的读取和写入操作- sdram with the controllor based on verilog
Platform: | Size: 358400 | Author: 钱军 | Hits:

[VHDL-FPGA-Verilog] 4port-sdram

Description: 4端口SDRAM控制器verilog程序-4-port SDRAM controller with verilog
Platform: | Size: 28672 | Author: xin | Hits:

[VHDL-FPGA-Verilog] UART_DMA

Description: 基于DE1的nios的串口sdram通信例程-Based on DE1' s nios serial communication routines sdram
Platform: | Size: 11353088 | Author: 李 | Hits:

[VHDL-FPGA-Verilog] Verilog_module

Description: micron 1G内存条verilog模型，对应具体信号为MT8HTF12864HZ-800，内存颗粒为MT47H128M8CF-25-micron 1G DDR2 SDRAM verilog module
Platform: | Size: 34816 | Author: | Hits:

[VHDL-FPGA-Verilog] tut_DE2_sdram_verilog

Description: DE2 sdram 的verilog 教学材料-tut_DE2 sdram verilog.
Platform: | Size: 391168 | Author: 陈文斌 | Hits:

[VHDL-FPGA-Verilog] sdram

Description: 在ISE环境中，利用verilog语言编写的SDRAM的控制，已经通过功能仿真，其中PLL部分并没有加入，使用时可以自行加入PLL模块。-Verilog language in the ISE environment, the use of SDRAM control, through functional simulation, which the PLL part and did not join, can join the PLL blocks.
Platform: | Size: 18432 | Author: 蔡青青 | Hits:

[OS program] SDRAM_verilog-serial-port

Description: FPGA对sdramd的操作，verilog语言设计！-FPGA SDRAM verilog
Platform: | Size: 44032 | Author: 张民 | Hits:

[Other] sdram-ctrl

Description: FPGA sdram 全页模式控制，用verilog语言写的，非常的精简，控制方便-FPGA sdram full-page mode control, written in verilog language is compact, easy to control
Platform: | Size: 6144 | Author: 方道门 | Hits:

[Windows Develop] DDR-SDRAM

Description: ddr sdram 控制器的源代码，内有vhdl和verilog。-DDR SDRAM controller
Platform: | Size: 903168 | Author: 何海山 | Hits:

[VHDL-FPGA-Verilog] SDRAM

Description: 在nios环境下，结合verilog语言开发，功能是往SDRAM里面写0-99并打印出来-Nios environment, combined with the verilog language development function is to write to the SDRAM inside 0-99 and print out
Platform: | Size: 16943104 | Author: zq | Hits:

[Other] sdram_mdl

Description: SDRAM的verilog程序控制模块，希望对大家有帮助-SDRAM verilog program control module, we want to help
Platform: | Size: 2196480 | Author: yxm | Hits:

[VHDL-FPGA-Verilog] sdram

Description: sdram控制器的Verilog描述 测试可用-the sdram controller Verilog description of test available
Platform: | Size: 8192 | Author: 刘备 | Hits:
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